Data transport for bit-interleaved streams supporting lane identification with invalid streams

ABSTRACT

A method for generating a channel stream. The method generally comprises the steps of (A) transforming a plurality of data streams, wherein every data stream entering the channel stream experiences a unique transformation and (B) serializing the data streams as transformed into the channel stream.

FIELD OF THE INVENTION

The present invention relates to a method and/or architecture for datastream multiplexing and demultiplexing generally and, more particularly,to data transport for bit-interleaved streams supporting laneidentification with invalid streams.

BACKGROUND OF THE INVENTION

The telecommunications industry uses serial data transmission to movelarge amounts of data from one point to another. Both conventionalPlesiochronous Digital Hierarchy (PDH) (i.e., T1/E1, T3/E3, etc.) andconventional Synchronous Optical Network/Synchronous Digital Hierarchy(SONET/SDH) systems multiplex or aggregate multiple source streamstogether to allow a single serial stream to carry multiple lower speedsources. The conventional systems multiplex the source streams basedupon character boundaries that force additional latency into the systemto allow the channels to be interleaved.

Recent backplane designs for transporting the source data streams areusing bit interleaving to reduce the latency, and lower the hardwareoverhead needed to handle the multiplexing and demultiplexing functions.Each source data stream is accepted as a serial stream, and the bits ofeach source data stream are sequentially bit-wise interleaved oraggregated to generate a single faster bit stream. Multiplexing ‘n’source data streams together produces a serial data stream that isn-times faster than each of the source data streams.

Where the aggregation function is desired but a logic overhead and delayof full framers are not available or wanted, the aggregation functioncan still occur by doing a bit-level or byte-level multiplexing of theindividual source data streams. Since there are generally nodistinguishing characteristics within the data itself to identify whichsource data stream is which, and the fact that more than one of thesource data streams can theoretically be carrying the same data, thereneeds to be some way to distinguish each of the source data streams forseparation at the receiver. Furthermore, there needs to be some way toresolve the received source data stream into particular lanes. When thesingle higher-speed serial data stream arrives at the destination, the‘n’ source data streams need to be separated. Standard clock recovery,data recovery, and demultiplex functions can provide the separation, butthe extracted (de-interleaved) serial data streams have no defaultorientation as to which source data stream should come out on a specificoutput bit-stream or lane.

Referring to FIG. 1, a block diagram of a conventional data streaminterleaving and de-interleaving system 10 is shown. The system 10inverts 12 a master source data stream (i.e., J) among several sourcedata streams (i.e., J–M) in a transmitter 14 prior to a serializer 16.The serializer 16 interleaves the source data streams J–M into a channelstream (i.e., T) that is transmitted through a channel 18. The inversion12 is effectively a lossless and reversible form of data manipulationthat allows the master source data stream J to be identified from theother source data streams K–M at a receiver 20.

At the receiver 20, the channel stream T is separated into multipledestination streams (i.e., P–S) using a deserializer 22. The destinationstreams P–S are passed to a barrel shifter 23 to allow each of thepossible destination streams P–S to be allocated to one of several lanes24 a–d. The particular destination stream P–S routed through the lane 24a is then inverted 26 to produce an inverted stream (e.g., W). Theinverted stream W is tested for characteristics of the master sourcedata stream J. Testing involves scanning 28 the inverted stream W for aspecific frame construct that may be present. If the frame construct isnot found, the barrel shifter 23 is ordered to rotate 30 to route a nextdestination stream P–S through the inverter 26. Scanning 28 and rotation30 are continued until the specific frame construct is found in theinverted stream W. In practice, the non-inverted source data streams K–Nshould not generate a match condition when inverted 26. However, theinverted master source data stream J (after the secondary inversion 26)will allow proper detection of the frame construct.

The system 10 works while the four source data streams J–M are alwayspresent. However, SONET/SDH equipment does not provide for each sourcedata stream J–M to originate from the same card, nor to be active all atthe same time. Therefore, it is possible for one or more of the sourcedata streams J–M to be missing or void of valid information. If achannel generating the master source data stream J ever goes away, thereceiver 20 has no way of identifying the proper destination of theresulting destination data streams P–S. Therefore, allocating thedestination streams P–S among the proper lanes 24 a–d becomesimpractical.

SUMMARY OF THE INVENTION

The present invention concerns a method for generating a channel stream.The method generally comprises the steps of (A) transforming a pluralityof data streams, wherein every data stream entering the channel streamexperiences a unique transformation and (B) serializing the data streamsas transformed into the channel stream.

The objects, features and advantages of the present invention includeproviding a method and/or architecture for data transport ofbit-interleaved streams supporting lane identification that may (i)operate with non-standard or invalid source channels, (ii) uniquelyidentify data streams containing similar or the same data at a receiveend, (iii) detect when some and/or all of the data streams may beinvalid/non-standard, and/or (iv) add no overhead to the transmitteddata.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the presentinvention will be apparent from the following detailed description andthe appended claims and drawings in which:

FIG. 1 is a block diagram of a conventional data stream interleavingsystem;

FIG. 2 is a block diagram of an example implementation of a transmittercircuit incorporating a preferred embodiment of the present invention;

FIG. 3 is a block diagram of an example implementation of a receivercircuit;

FIG. 4 is a flow diagram of a method for generating a channel stream;

FIG. 5 is a flow diagram of a method for adding a valid data stream to achannel stream;

FIG. 6 is a flow diagram of a method for recovering data streams at areceiver circuit;

FIG. 7 is a flow diagram of a method for detecting a reference patternin a receiver circuit;

FIG. 8 is a block diagram of an example implementation of a multi-bittransformation circuit;

FIG. 9 is a block diagram of a second example implementation of atransformation circuit; and

FIG. 10 is a block diagram of a third example implementation of atransformation circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 2, a block diagram of an example implementation of acircuit 100 is shown incorporating a preferred embodiment of the presentinvention. The circuit 100 may be implemented as a transmitter circuit.The transmitter circuit 100 may be configured to interleave multiplesignals or source data streams (e.g., J1–M1) received at an input 101into a single signal or stream (e.g., T). The stream T may be referredto as a high-speed stream, a transmission stream, a transport stream,and/or a channel stream. Each source data stream J1–M1 may besimultaneously transformed by a unique transformation, synchronized ifappropriate, and then serialized to generate the channel stream T. Thetransformations may be reversible (e.g., lossless) to permit recovery ofthe original source data streams J1–M1 at a receiving end.

The transmitter circuit 100 generally comprises multiple circuits 102a–d, multiple register circuits 104 a–d, and a serializer circuit 106.The transmitter circuit 100 may optionally comprise a scan circuit 108and a pattern generator circuit 110. The transmitter circuit 100 may bedesigned to receive more or less than four source data streams J1–M1 tomeet the design criteria of a particular application. Furthermore, thetransmitter circuit 100 may be configured to multiplex the source datastreams J1–M1 into multiple channel streams T to meet the designcriteria of a particular application. The four-to-one multiplexing shownmay be considered as an example for illustrative purposes.

The circuits 102 a–d may be configured as transformation circuits. Eachtransformation circuit 102 a–d may perform a modification to arespective source data stream J1–M1 to generate transformed data streams(e.g., J2–M2). The modifications performed by each transformationcircuit 102 a–d may be unique among the other modifications ortransformations. In one embodiment, the modifications may be designed aszero-overhead modifications, meaning that a same amount of data may begenerated by the transformation circuits 102 a–d as received by thetransformation circuits 102 a–d. In another embodiment, themodifications may introduce some overhead to the transformed datastreams J2–M2.

Each register circuit 104 a–d may be configured as a single flip-flop inthe form of a pipeline register present in each data stream. Theregister circuits 104 a–d may be optionally implemented to keeplatencies matched for (e.g., synchronize) all four transformed datastreams J2–M2 where appropriate. Each register circuit 104 a–d may beconfigured to store a unit of a respective transformed data streamJ2–M2. The unit may be defined as a bit, a nibble, a byte, a 9-bit word,a 10-bit word, a 16-bit word, a 32-bit word, a 64-bit word, a frame, orsimilarly bounded amount of data. More or fewer registers may be addedto each stream without effect on the data content or operation of thecircuit, with the only impact being latency of data transferred thoughthe circuit 100. In one embodiment, the storing may be performed in aserial fashion storing a single bit at a time. In another embodiment,the storing may be performed in a sequential fashion where several bitsmay be stored at a time. Presentation of the stored data may beperformed serially, in parallel, or sequentially. The register circuits104 a–d may present stored data streams (e.g., J3–M3) respectively tothe serializer circuit 106.

The serializer circuit 106 may receive each of the stored data streamsJ3–M3 in register circuits 112 a–d. The register circuits 112 a–d mayreceive the stored data streams J3–M3 in the same fashion (serial orparallel) as presented by the register circuits 104 a–d. The registercircuits 112 a–d may be interconnected to generate the channel stream Tfrom the stored data streams J3–M3. In one embodiment, the channelstream T may be implemented as a single-bit wide serial data stream. Inanother embodiment, the channel stream T may be implemented as amulti-bit wide data stream, multiple signals, and/or one or more signalshaving multiple levels and/or phases.

The following transformation examples may be based on a single-bit widesource data streams J1–M1. The transformation circuit 102 a may beconfigured to perform an inverting transformation. The transformationcircuit 102 a may comprise an inverter 114 configured to receive thesource data stream J1 and generate the transformed data stream J2. Theinverting transformation may be defined by equation 1 as follows:G(X)=−1  Eq. (1)

The transformation circuit 102 b may be configured to perform an NRZIencode operation. An XOR gate 116 may receive the source data stream K1and a history data stream (e.g., K4) as inputs to generate thetransformed data stream K2. The transformed data stream K2 may becaptured in a register circuit 128 to generate the history data streamK4. Thus, the data stream K2 may be a non-return to zero invert-on-one(NRZI) modification of the source data stream K1. The NRZItransformation may be defined by equation 2 as follows:G(X)=X+1  Eq. (2)

The transformation circuit 102 c may be configured to perform aninverted NRZI encode operation on the source data stream L1. Inversionof the source data stream L1 may be provided by an inverter 118. Theinverter 118 may be connected in series with an XOR gate 120 that alsoreceives a history data stream (e.g., L4). The XOR gate 120 may generatethe transformed data stream L2. The transformed data stream L2 may becaptured in a register circuit 129 to generate the history data streamL4. Therefore, the data stream L2 may be an NRZI transformation of theinverted source data stream L1. The inverted NRZI transformation may bedefined by equation 3 as follows:G(X)=X−1  Eq. (3)

The transformation circuit 102 d may be configured to perform a unitytransformation on the source data stream M1. The unity transformationmay be implemented as a non-inverting amplifier (not shown) or aconductor 122 (shown) conveying the source data stream M1 to theregister circuit 104 d. Therefore, the transformed data stream M2 may beidentical to the source data stream M1. The unity transformation may bedefined by equation 4 as follows:G(X)=1  Eq. (4)

In general, there may be ‘n’ transformation circuits 102 a–d, one foreach of the ‘n’ source data streams J1–M1. In one embodiment, n−1 of thetransformations may be implemented with active logic circuitry while asingle transformation (e.g., in the transformation circuit 102 d) may beimplemented with passive circuitry or may be absent. Each transformationmay be unique from the other transformations. Furthermore, eachtransformation may be reversible through complementary logic at areceiver (FIG. 3). Each transformation circuit 102 a–d may beimplemented to provide a single step or a multi-step transformation. Inthe domain of logic, there may be effectively a large number of thelogic transforms that may be applied to any given source data streamJ1–M1. The transformations may include, but are not limited to, logictransformations, polynomial transformations, synchronous scramblertransformations, encryption transformations, and the like. Theuniqueness and reversibility of the transformations generally allowsevery source data stream J1–M1 to be distinguished and identified at thereceiver when at least one of the source data streams J1–M1 may bevalid.

The pattern generator circuit 110 may be included in the transmittercircuit 100 for situations where all of the source data streams J1–M1may be invalid, non-standard, and/or none of the source data streamsJ1–M1 may contain a predetermined reference pattern expected by thereceiver. The pattern generator circuit 110 may be configured togenerate a valid source data stream (e.g., N1) having the predeterminedreference pattern either continuously or when appropriate. The sourcedata stream N1 may be inserted into the serializer 106 in place of oneof the stored data streams J3–M3. For example, a multiplexer 124 may beused to replace the (invalid or non-standard) stored data stream M3 withthe source data stream N1. Control of the multiplexer 124 may beprovided from the pattern generator circuit 110, the scan circuit 108,or a host (not shown). In another embodiment, the source data stream N1may be inserted in place of one of the source data streams J1–M1 beforethe transformation circuits 102 a–d.

The pattern generator circuit 110 may be directed by the host. Controlby the host may be provided through a set of signals (e.g., STATUSa–d).The host may mark each signal STATUSa–d with a valid orinvalid/non-standard condition of a respective source data stream J1–M1.If all of the source data streams J1–M1 are marked invalid/non-standardby the host, the pattern generator circuit 110 may generate and presentthe valid source data stream N1.

Control of the multiplexer 124 may be provided from the scan circuit 108through a signal (e.g., CMD1). The scan circuit 108 may monitor thesource data streams J1–M1 for the predetermined reference pattern. Ifthe predetermined reference pattern is found in at least one source datastream J1–M1, the scan circuit 108 may generate the signal CMD1 in avalid state. The valid state of the signal CMD1 may instruct themultiplexer 124 to route the source data stream M3 to the serializercircuit 106. If the predetermined reference pattern is not found in anyof the source data streams J1–M1, the scan circuit 108 may generate thesignal CMD1 in an invalid state. The invalid state of the signal CMD1may instruct the multiplexer 124 to route the source data stream N1 inplace of the stored data stream M3 (as shown), one of the source datastreams J1–M1, or one of the other stored data streams J3–L3.

The predetermined reference pattern or other validation signature may bespecific to each particular application. For example, in a SynchronizedOptical Network/Synchronous Digital Hierarchy (SONET/SDH) applicationand/or an Optical Transport Network (OTN), a frame construct may be usedas the predetermined reference pattern. In one embodiment, thepredetermined reference pattern may comprise a sequence of consecutiveA1 characters followed by consecutive A2 characters. In anotherembodiment, the predetermined reference pattern may comprise threeconsecutive A1 characters followed by three consecutive A2 characters.Other reference patterns may be implemented to meet the design criteriaof a particular application.

The scan circuit 108 generally scans each of the source data streamsJ1–M1 continuously. Per SONET/SDH, the A1/A2 characters may be repeatedevery 125 microseconds (μs). Therefore, the scan circuit 108 may waitfor 125 μs, or slightly longer (e.g., ≧1 bit after 125 μs) beforedetermining that the framing pattern construct may be missing from asource data stream J1–M1. Other scan periods may be implemented todetermine if and when the predetermined reference pattern becomesabsent.

Referring to FIG. 3, a block diagram of an example implementation of acircuit 130 is shown. The circuit 130 may be implemented as a receivercircuit. The receiver circuit 130 may be configured to de-interleave anddeserialize the channel stream T into multiple received data streams(e.g., P1–S1). Each received data stream P1–S1 may be routed to a uniquetransformation to undo the transformations of the transformationcircuits 102 a–d in the transmitter circuit 100. While the received datastreams P1–S1 may be routed to the correct reverse transformations, theoriginal source data streams J1–M1 may be reproduced at an output 131 ofthe receiver circuit 130.

The receiver circuit 130 generally comprises a deserializer circuit 132,a circuit 134, multiple register circuits 136 a–d, multiple circuits 138a–d, a scan circuit 140, and a rotate circuit 142. The circuit 134 maybe implemented as a multiplexer circuit or a barrel shifter circuit.Each register circuit 136 a–d may be configured as n (where n is aninteger) flip-flops in the form of pipeline registers present in eachdata stream. Each circuit 138 a–d may be implemented as a transformationcircuit.

The deserializer circuit 132 may be configured to convert the channelstream T into the received data streams P1–S1. The deserializer circuit132 generally comprises multiple register circuits 144 a–d. Eachregister circuit 144 a–d may be coupled together to receive the channelstream T in a serial fashion. Reception may match the width of thechannel stream T. For example, a single-bit wide channel stream T may bereceived by the register circuit 144 d one bit at a time. A multi-bitwide channel stream T may be received several bits at a time. As eachnew bit or bits are received, the older bits may be shifted seriallydown through the register circuits 144 a–d. When all of the registercircuits 144 a–d are generally full, the contents of the registercircuits 144 a–d may be presented to the barrel shifter circuit 134 asportions of the received data streams P1–S1. Each received data streamP1–S1 may be implemented as a single-bit wide or multiple-bit widesignal.

The barrel shifter circuit 134 may be operational to route each of thereceived data streams P1–S1 to one of several lanes 146 a–d of thereceiver circuit 130. The received data streams P1–S1 may be referred toas shifted data streams W1–Z1 while residing in the lanes 146 a–d. Anallocation of the received data streams P1–S1 to the shifted datastreams W1–Z1 may be determined by the shifting or multiplexingfunctionality provided by the barrel shifter circuit 134. For example,if the received data stream P1 is routed to the shifted data stream Y1in the lane 146 c, the other received data streams Q1, R1, and S1 may berouted to the shifted data streams Z1, W1, and X1 respectively.

The register circuits 136 a–d may keep latencies matched for all fourshifted data streams W1–Z1. Each register circuit 136 a–d may beconfigured to store a unit or portion of the respective shifted datestream W1–Z1. The unit may be defined to be the same as in thetransmitter circuit 100. In one embodiment, storing may be performed ina serial fashion storing a single bit at a time. In another embodiment,storing may be performed sequentially where several bits are stored at atime. Presentation of the stored data may be performed serially, inparallel, or sequentially. The register circuits 136 a–d may presentstored data streams (e.g., W2–Z2) respectively to the transformationcircuits 138 a–d.

Each transformation circuit 138 a–d may be designed to perform atransformation unique among the other transformations. Generally, eachof the transformation circuits 138 a–d in the receiver 130 may implementa reverse transformation of a complimentary transformation circuit 102a–d in the transmitter circuit 100. Furthermore, the assignment of thetransformation circuits 138 a–d to the lanes 146 a–d may match theassignment of the transformation circuits 102 a–d to the inputs of theserializer circuit 106.

The transformation circuit 138 a may be configured to perform aninverting transformation. The transformation circuit 138 a may comprisean inverter 148. The inverter 148 may be configured to receive thestored data stream W2 and generate a transformed data stream W3.

The transformation circuit 138 b may be configured to perform an NRZIdecode operation. An XOR logic gate 150 may receive the stored datastream X2 and a history data stream (e.g., X4) as inputs to generate atransformed data stream X3. The stored data stream X2 may be captured ina register circuit 158 to generate the history data stream X4.Therefore, the stored data stream X3 may be an NRZI decodetransformation of the shifted data stream X1.

The transformation circuit 138 c may be configured to perform aninverted NRZI decode operation. An XNOR operation may be provided by anXOR logic gate 152 in series with an inverter 154. The XOR logic gate152 may receive the stored data stream Y2 and a history data stream(e.g., Y4) as inputs. The inverter 154 may invert the output signalgenerated by the XOR logic gate 152. The stored data stream Y2 may becaptured in a register circuit 159 to generate the history data streamY4. Therefore, a transformed data stream Y3 may be an inverted NRZItransformation of the shifted data stream Y1.

The transformation circuit 138 d may be configured to perform a unitytransformation on the stored data stream Z2. The unity transformationmay be implemented as a non-inverting amplifier (not shown) or aconductor 156 (shown) conveying the stored data stream Z2. Therefore, atransformed data stream Z3 may be identical to the stored data streamZ2.

Similar to the transmitter circuit 100, the receiver circuit 130 mayhave ‘n’ transformation circuits 136 a–d, one for each of the ‘n’shifted data streams W1–Z1. In one embodiment, n−1 of thetransformations may be implemented with active logic circuitry while asingle transformation (e.g., provided by the transformation circuit 138d) may be implemented with passive circuitry or may be absent. Eachtransformation may be unique among the other transformations. Eachtransformation may also be a reverse of the respective transformationlogic in the transmitter circuit 100. Each transformation circuit 138a–d may be implemented to provide a single step or a multi-steptransformation. In the domain of logic, there may be effectively a largenumber of the logic transforms that may be applied to any given shifteddata stream W1–Z1. The transformations may include, but are not limitedto logic transformations, polynomial transformations, synchronousde-scrambler transformations, decryption transformations, and the like.The uniqueness and reversibility of the transformations generally allowsevery shifted data stream W1–Z1 to be distinguished at the receivercircuit 130 while at least one of the shifted data streams W1–Z1 may bevalid.

The scan circuit 140 may receive one or more of the transformed datestreams W3–Z3. The scan circuit 140 may generate a signal (e.g., CMD2).The scan circuit 140 may also generate multiple status signals (e.g.,VALIDa–d), one for each lane 146 a–d.

The scan circuit 140 may search each received transformed data streamW3–Z3 for the predetermined reference pattern. In the embodiment wherethe predetermined reference pattern may be the frame construct of aSONET/SDH data stream, the scan circuit 140 may scan each transformeddata stream W3–Z3 for at least slightly longer (e.g., ≧1 bit) than the125 μs frame rate. If a valid predetermined reference pattern may beabsent in all of the scanned transformed data streams W3–Z3 after a setperiod or number of bits have been scanned, the scan circuit 140 maygenerate the signal CMD2 in the invalid state. The invalid state of thesignal CMD2 may instruct the rotate circuit 142 to command a rotation ofthe barrel shifter circuit 134. The rotate circuit 142 may generate asignal (e.g., CMD3) to instruct the barrel shifter circuit 134 toreroute or shift the received data streams P1–S1 by one or more lanes146 a–d. For example, the received data stream P1 may be rerouted fromthe lane 146 b to the lane 146 c. Thereafter, the shifted data stream Y1may match the received data stream P1. Scanning and rotating may becontinued until the predetermined reference pattern is generallydetected in at least one of the transformed data streams W3–Z3. When thescan circuit 140 detects the predetermined reference pattern in at leastone of the transformed data streams W3–Z3, the scan circuit 140 maygenerate the signal CMD2 in the valid state. The signal CMD2 in thevalid state may instruct the rotate circuit 142 to hold the signal CMD3at a current value.

An advantage of the present invention as compared to the conventionalsystem 10 may be that the receiver circuit 130 may not rely on apresence of a valid single master source data stream. If any one or moreof the transformed data streams W3–Z3 contains the reference pattern,the receiver circuit 130 may identify the correct alignment of thereceived data streams J1–S1 to the lanes 146 a–d. Therefore, thetransmitter circuit 100 and receiver circuit 130 may remain synchronizedwith each other while one or several of the source data streams J1–M1may be absent, invalid, non-standard, and/or lack the reference pattern.

For each lane 146 a–d monitored, the scan circuit 140 may generate arespective signal VALIDa–d. The scan circuit 140 may generate therespective signal VALIDa–d in the invalid state where the scan circuit140 fails to find the predetermined reference pattern in the associatedtransformed data stream W3–Z3. The scan circuit 140 may generate therespective signal VALIDa–d in the valid state where the predeterminedreference pattern may be detected in the associated transformed datastream W3–Z3. The signals VALIDa–d may be used at the receiver end toindicate status of the received data streams P1–S1.

The barrel shifter circuit 134 may be useful in the receiver circuit 130since the deserializer circuit 132 may have no knowledge of how theindividual transformed data streams J3–M3 are interleaved into thechannel stream T. By stepping through each possible allocation of thereceived data streams P1–S1 through the various transformation circuits138 a–d, a correct match or shifting between the received data streamsP1–S1 and the shifted data streams W1–Z1 may be determined by the scancircuit 140.

While the barrel shifter circuit 134 does not provide the correct match,the various transformation circuits 138 a–d generally may not properlyreverse the transformations performed in the transmitter circuit 100. Incontrast, while the barrel shifter circuit 134 provides the correctrouting of the received data streams P1–S1 to the shifted data streamsW1–Z1, the transformation circuits 138 a–d may reverse thetransformations performed on the source data streams J1–M1 in thetransmitter circuit 100. Each transformed data stream W3–Z3 may thenrepresent an accurate reproduction of a respective source data streamJ1–M1. Therefore, for each source data stream J1–M1 incorporating thepredetermined reference pattern generally results in the predeterminedreference pattern appearing in the associated transformed data streamW3–Z3. The scan circuit 140 may detect the predetermined referencepatterns and maintain the present condition of the barrel shiftercircuit 134. As a result, even if only one transformed data stream W3–Z3has the predetermined reference pattern, then all of the transformeddata streams W3–Z3 may be allocated to the proper lanes 146 a–d, andundergo the correct reverse transformation. Therefore, each transformeddata stream W3–Z3 may be identifiable with the source data streams J1–M1based upon the final lane allocation. The identification may be usefulwhere two or more of the source data streams J1–M1 carry similar, nearlyidentical, or even identical information that may make distinguishingthe data streams difficult.

Referring to FIG. 4, a flow diagram of a method for generating thechannel stream T is shown. The method generally begins with reception ofthe one or more source data streams from the host (e.g., block 160). Thetransmitter circuit 100 then performs a unique transformation on each ofthe data streams (e.g., block 162). After experiencing thetransformations, the data streams may be buffered or stored, ifappropriate, to equalize the latency for all of the data streams (e.g.,block 164). After storage, the data streams may be serialized tointerleave the individual data streams to generate the channel stream T(e.g., block 166). Finally, the channel stream T may be transmitted tothe receiver circuit 130 (e.g., block 168).

Referring to FIG. 5, a flow diagram of a method for adding a valid datastream to the channel stream T is shown. The method may begin either byscanning the source data streams for the reference pattern (e.g., block170) or by the host marking all of the source data streams asinvalid/non-standard (e.g., block 172). If scanning of the source datastreams identifies at least one valid data stream (e.g., the YES branchof decision block 174), the multiplexer 124 may address or route thesource data stream (e.g., block 176). Continuously, or while all of thedata streams are generally invalid/non-standard (e.g., the NO branch ofdecision block 174), as determined by the scan circuit 108 and/or thehost, the pattern generator circuit 110 may generate a valid data stream(e.g., block 178). The valid data stream may then be inserted in placeof one or more of the data streams (e.g., block 180).

Referring to FIG. 6, a flow diagram of a method for recovering the datastreams at the receiver circuit 130 is shown. The method may begin uponreceipt of a portion of the channel stream T sufficient for thedeserializer circuit 132 to operate (e.g., block 182). The deserializercircuit 132 may then deserialize and de-interleave the channel stream Tinto multiple data streams (e.g., block 184). The barrel shifter circuit134 may route the individual data streams among the lanes (e.g., block186). The data streams may then be stored or buffered in each lane(e.g., block 188). Unique reverse transformations may be applied to eachdata stream (e.g., block 190). Finally, the transformed data streams maybe presented by the receiver circuit 130 to other circuitry (e.g., block192).

Referring to FIG. 7, a flow diagram of a method for detecting thereference pattern in the receiver circuit 130 is shown. Detection mayinclude scanning one, several, or all of the data streams aftershifting, buffering, and transforming (e.g., block 194). A status signalmay be generated for each lane to indicate if the data stream in thelane may be valid or not (e.g., block 196). If at least one validreference pattern has been detected (e.g., the YES branch of decisionblock 197), shifting may be halted at a current position and scanningcontinued in case the reference pattern or patterns disappear. If novalid streams have been detected (e.g., the NO branch of decision block197), a duration may be checked. If an entire frame has not been scanned(e.g., the NO branch of decision block 198), scanning may continue(e.g., block 194). If an entire frame has been scanned without detectingat least one reference pattern (e.g., the YES branch of decision block198), the scan circuit 140 may instruct the rotate circuit 142 tocommand the barrel shifter circuit 134 to shift the data streams (e.g.,block 200). Scanning and shifting may continue until all possible shiftcombinations between the received data signals and the lanes have beentested. If no valid data streams are detected, the barrel shiftercircuit 134 may rotate back to an initial configuration and scanning maycontinue.

Referring to FIG. 8, a block diagram of an example implementation of amulti-bit transformation circuit 202 is shown. The transformationcircuit 202 may be implemented in the transmitter circuit 100 and/or inthe receiver circuit 130. The transformation circuit 202 generallycomprises a circuit 204 in series between a serial-to-parallel convertercircuit 206 and a parallel-to-serial converter circuit 208. By way ofexample, a single-bit wide signal or data stream (e.g., C) may bereceived by the serial-to-parallel converter circuit 206. Theserial-to-parallel converter circuit 206 may store a unit comprising ‘n’bits of the data stream C. The resulting n-bit wide data stream (e.g.,D) may be transferred to the circuit 204. The circuit 204 may transformthe n-bit data stream D into an m-bit signal (e.g., E). Thetransformation may be performed on the entire unit all at once. Theresulting m-bit data stream E may be presented to the parallel-to-serialconversion circuit 208. The parallel-to-serial conversion circuit 208may convert the data stream E back into a single-bit data stream (e.g.,F).

A value of ‘m’ may be equal to or greater than a value of ‘n’ in thetransmitter circuit 100. The value of ‘m’ may be less than or equal tothe value of ‘n’ in the receiver circuit 130. The transformation may bea reversible block conversion using a lookup table and/or an appropriatemapping. A potential use of an n-bit to m-bit block conversion may be tochange long sequences of all logical ones or all logical zeros intopatterns having some logical ones and some logical zeros (e.g., reduce aDC component of a signal). Examples of reversible block conversions maybe 8B/10B and 10B/8B block conversions. In another example, the blockconversion may be implemented as an encryption in the transmittercircuit 100 and as a decryption in the receiver circuit 130. Other blockconversions may be implemented to meet the design criteria of aparticular application.

Referring to FIG. 9, a block diagram of a second example implementationof a transformation circuit 210 is shown. The transformation circuit 210may be suitable for implementation in the transmitter circuit 100. Thetransformation circuit 210 generally comprises multiple registers 212a–d and multiple adders 214 a–b.

The registers 212 a–d may be configured as a serial shift register withthe first register 212 a receiving a signal (e.g., C4). A firstmodulo-two adder 214 a may sum the signal C4 with an output signal(e.g., C1) from the third register 212 c to generate a signal (e.g., S).A second modulo-two adder 214 b may sum the output signal (e.g., C0) ofthe fourth register 212 d and the signal S to generate a transformedsignal (e.g., F). The transformation G(X) provided by the circuit 210may define a polynomial as shown in equation 5 as follows:G(X)=1+X+X ⁴  Eq. (5)

Referring to FIG. 10, a block diagram of a third example implementationof a transformation circuit 216 is shown. The transformation circuit 216may be suitable for implementation in the receiver circuit 130. Thetransformation circuit 216 may provide a reverse transformation of thetransformation circuit 210.

The transformation circuit 216 generally comprises multiple registers218 a–d and multiple adders 220 a–b. The registers 218 a–d may beconfigured to form a serial shift register. The first modulo-two adder220 a may sum the signal F (generated by the transformation circuit 210)with an output signal (e.g., V) from the second adder 220 b. The secondmodulo-two adder 220 b may sum an output signal (e.g., H1) generated bythe third register 218 c and an output signal (e.g., H0) generated bythe fourth registers 218 d to generate the output signal V. The sumgenerated by the first modulo-two adder 220 a (e.g., H4) may be providedto the first register 218 a and may also reproduce the original signalC4.

Referring to FIGS. 2 and 3, an example implementation of the transmittercircuit 100 may be to aggregate four OC12 bit streams that may betransported across an equivalent of an OC48 serial link. The channelstream T may be segregated back into four OC12 bit streams by thereceiver circuit 130. By appropriate setting of the barrel shiftercircuit 134, an allocation of the received OC12 bit streams may bedirected to the proper lanes 146 a–d. Therefore, each uniquetransformation performed in the transmitter circuit 100 may becompletely reversed by the matching transformation in the receivercircuit 130.

More or fewer data streams may be multiplexed together by changing asize of the serialization/deserialization (SERDES) functions provided bythe serializer circuit 106 and the deserializer circuit 132.Furthermore, the logic transform functions may be moved to any datastream in any order. For example, the unity transformation may beassociated with the second source data stream K1 in the transmittercircuit 100 and the second shifted data stream X1 in the receivercircuit 130. In another embodiment, all of the data streams (instead ofjust n−1 data streams) may undergo non-unity transformations.

Interfaces to the serializer circuit 106 and the deserializer circuit132 may be some multiple (other than 1) of a number of bit streamsmerged together. For example, the SERDES interfaces may be 8-bits wideand still accept and deliver four single-bit data streams. The multiplemay also be configured as a non-integer by implementing gearbox logic totransform from a first width domain to a second width domain. Otherdesigns may be implemented to meet the design criteria of a particularapplication.

The various signals of the present invention are generally “on” (e.g., adigital HIGH, valid, or 1) or “off” (e.g., a digital LOW, invalid, or0). However, the particular polarities of the on (e.g., asserted) andoff (e.g., de-asserted) states of the signals may be adjusted (e.g.,reversed) accordingly to meet the design criteria of a particularimplementation. Additionally, inverters may be added to change aparticular polarity of the signals. As used herein, the term“simultaneously” is meant to describe events that share some common timeperiod but the term is not meant to be limited to events that begin atthe same point in time, end at the same point in time, or have the sameduration.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. A method for generating a channel stream, comprising the steps of:(A) transforming a plurality of data streams in parallel with aplurality of transformations, wherein a unique one of saidtransformations is provided for each respective one of said datastreams; and (B) serializing said data streams as transformed into saidchannel stream.
 2. The method according to claim 1, further comprisingthe step of synchronizing a plurality of units of data, one of saidunits from each respective one of said data streams, with each otherprior to serializing.
 3. The method according to claim 2, wherein atleast one of said unique transformations receives a respective one ofsaid units as an input.
 4. The method according to claim 1, wherein atleast one of said transformations comprises a plurality of sequentialtransformations.
 5. The method according to claim 1, wherein at leastone of said unique transformations comprises a block substitutiontransformation.
 6. The method according to claim 1, wherein at least oneor said unique transformations comprises a polynomial transformation. 7.The method according to claim 1, wherein at least one of said uniquetransformations comprises an encryption transformation.
 8. The methodaccording to claim 1, further comprising the step of detecting when allof said data streams are invalid.
 9. The method according to claim 8,further comprising the steps of: generating a valid data stream; andreplacing one of said data streams with said valid data stream.
 10. Themethod according to claim 1, further comprising the steps of:deserializing said channel stream into a plurality of received datastreams; routing each one of said received data stream into a respectiveone of a plurality of lanes; and transforming said received data streamsin parallel with a plurality of inverse transformations, wherein aunique one of said inverse transformations is provided for eachrespective one of said lanes, to recover said data streams.
 11. A methodfor demultiplexing a channel stream, comprising the steps of: (A)deserializing said channel stream into a plurality of data streams; (B)routing each one of said data stream into a respective one of aplurality of lanes; and (C) transforming said data streams in parallelwith a plurality of transformations, wherein a unique one of saidtransformations is provided for each respective one of said lanes. 12.The method according to claim 11, further comprising the step ofscanning at least one of said data streams for a reference bit pattern.13. The method according to claim 12, further comprising the step ofrerouting said data streams among said lanes in response to an absenceof said reference bit pattern.
 14. The method according to claim 11,further comprising the step of scanning each of said data streams for areference bit pattern.
 15. The method according to claim 14, furthercomprising the step of asserting a respective valid signal for each oneof said data streams in which said reference bit pattern is found. 16.The method according to claim 11, further comprising the step of storinga plurality of units of data in parallel, one unit from each respectiveone of said data streams, prior to transforming.
 17. The methodaccording to claim 16, wherein at least one of said transformationsreceives a respective one of said units as an input.
 18. The methodaccording to claim 11, wherein at least one of said transformationscomprises a decryption transformation.
 19. The method according to claim11, wherein at least one of said transformations comprises a non-returnto zero invert-on-one transformation.
 20. A circuit comprising: meansfor transforming a plurality of data streams in parallel with aplurality of transformations, wherein a unique one of saidtransformations is provided for each respective one of said datastreams; and means for serializing said data streams as transformed intoa channel stream.
 21. A circuit comprising: means for deserializing achannel stream into a plurality of data streams; means for routing eachone of said data stream into a respective one of a plurality of lanes;and means for transforming said data streams in parallel with aplurality of transformations, wherein a unique one of saidtransformations is provided for each respective one of said lanes.